1. Field of the Invention
The present invention relates to a method for manufacturing a solid-state imaging device.
2. Description of the Related Art
A CMOS image sensor includes a logic circuit whose logical portion includes a transistor having a gate electrode, and the gate length of the gate electrode is most miniaturized.
If the level of transistor miniaturization lies before the 90 nm generation defined by the roadmap for CMOS LSI, in general, desired characteristics can be imparted to the transistor without forming an offset spacer. The offset spacer, which is formed on the sidewall of the gate electrode, is intended to adjust the overlap length (ΔL) of the source/drain extension regions and the gate electrode of the transistor.
In order to install 90 nm generation transistors or later to a solid-state imaging device with a practical ion implantation apparatus or by a practical heat treatment technique, however, ion implantation is performed to form source/drain extension regions after forming the offset spacer.
In general, the following two approaches can be applied:
(1) Combining a manufacturing process of CMOS logic circuits before the 90 nm generation and a manufacturing process not using the offset spacer; and
(2) Combining a process using a manufacturing process of CMOS logic circuits of the 90 nm generation or later and a manufacturing process using the offset spacer.
In the above approach (2), offset spacers 131 are formed on all the gate electrodes 110 and 120 without differentiating between the gate electrodes 110 of the transistors in the logic circuit region 114 and the gate electrodes 120 of the transistors of the peripheral (I/O) circuit and pixel region 112, as shown in FIG. 14.
The regions of the silicon substrate where source/drain regions of pixel transistors, particularly of the amplification transistor, are to be formed are damaged by etching for forming offset spacers. If the substrate is damaged by etching, noise of the amplification transistor is increased. Also, if the region of the silicon substrate where a photoelectric conversion portion is to be formed is damaged by etching, white spots may be increased.
In a process similar to the above (2), sidewall insulating films used for forming the source/drain regions are formed on the sidewalls of the gate electrodes. For example, Japanese Unexamined Patent Application Publication No. 2006-210583 discloses that when the sidewall insulating films are formed, an insulating layer intended for the sidewall insulating films is left on a photoelectric conversion region (for example, photodiode). The insulating layer left on the photoelectric conversion region is intended to prevent a silicide from being formed on the photoelectric conversion region by silicidation performed after forming the source/drain regions.